EDN

DRAM controller throughput may be the next key to SoC performance

As SoC architects make the transition from CPU-centric designs with a single major processor to multiprocessing designs in which many processing peers carry on in parallel, efficient use of external ...
Hackaday

dram controller

Ask anyone to name a first-generation home computer from the 1970s, and they’ll probably mention the likes of the Altair 8800 and IMSAI 8080. But those iconic machines weren’t the only options ...
Forbes

Spin Memory Selector Improves DRAM, ReRAM And MRAM Density, New Microchip SSD Controller

Spin Memory, a magnetic random-access memory (MRAM) startup announced a new semiconductor technology that could allow a dramatic improvement in DRAM as well as emerging memory technologies, such as ...
Semiconductor Engineering

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)

A new technical paper titled “A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations” was published by ...
EDN

The IP market reflects new realities in DRAM control for SoCs

One of the things to come out of an earlier posting on DRAM controllers for SoC design was an interview with the marketing folks at Synopsys’s IP group (see here, for instance.) They are just ...
Electronic Design

A Summary Of The DDR Memory Controller Standard—Wait, There Isn’t One!

The number of systems-on-a-chip (SoCs) that require an interface to off-chip memory is increasing. As a result, more and more designers are turning to double-data-rate (DDR) SDRAM interfaces such as ...