When a CMOS circuit is in an idle state there is still some static power dissipation–a result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic ...

PMOS transistors are less vulnerable to substrate noise since they’re placed in separate wells; designers implement guard rings to attenuate the substrate noise propagation. However, substrate noise ...

X-FAB has added three new low-noise transistors to its 180nm process node: a 1.8 V low-noise NMOS, a 3.3 V low-noise NMOS and a 3.3 V low-noise PMOS – all of which offer drastically reduced flicker ...

For years—decades, in fact—the NMOS transistor world has been on cruise control. NMOS is naturally faster and its performance has scaled better than PMOS. PMOS has had a cost advantage. But lately, it ...

Designers of electronics and communications systems are constantly faced with the challenge of integrating greater functionality on less silicon area. Many of the system blocks – such as power ...

X-Fab Silicon Foundries has added 375V power transistors to the devices available from its 180nm deep trench isolation BCD-on-SoI platform chip fab. The second generation of its XT018 super-junction ...

Advanced process technologies, such as 90nm, 65nm, 45nm and below, present significant power management challenges for high performance semiconductors. Chip designers face increasing challenges in ...

I was testing a circuit and found many discrepancies from the paper design I used to create it. The dynamics of the circuit were a bit unexpected, andthe noise level was much larger than required. I ...