EDN

Memory controller reference design targets edge AI and video processing

Lattice Semiconductor Corp. and Etron Technology Inc. have released a memory controller reference design for Etron’s low-pin-count RPC DRAM for low-power edge AI and video-processing applications that ...
Semiconductor Engineering

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)

A new technical paper titled “A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations” was published by ...
insideHPC

Intel tackles FPGA HPC Memory Bottleneck

Intel is aiming to tackle the challenges of increasing memory bandwidth for HPC applications with an FPGA that includes High Bandwidth Memory DRAM (HBM2). Intel recently announced the availability of ...
datanami.com

IntelliProp Announces Gen-Z Persistent Memory Controller Combining DRAM and NAND

LONGMONT, Colo., Aug. 8, 2017 — IntelliProp, Inc., a leader in innovative Intellectual Property (IP) Cores and semiconductors for Data Storage and Memory applications, announced today the IPA-PM185-CT ...
New Electronics

AMD validates Infineon’s HYPERRAM memory for FPGA evaluation kit

Infineon Technologies has confirmed that AMD successfully tested its 64 Mb HYPERRAM memory and HYPERRAM controller IP with the AMD Spartan UltraScale+ FPGA SCU35 Evaluation Kit. HYPERRAM memory ...
insideHPC

Intel Unveils Industry’s First FPGA Integrated with HBM Memory

Today Intel announced the availability of the Intel Stratix 10 MX FPGA, the industry’s first field programmable gate array (FPGA) with integrated High Bandwidth Memory DRAM (HBM2). By integrating the ...
Business Wire

Intel Unveils Industry’s First FPGA Integrated with High Bandwidth Memory Built for Acceleration

SANTA CLARA, Calif.--(BUSINESS WIRE)--Intel today announced the availability of the Intel® Stratix® 10 MX FPGA, the industry’s first field programmable gate array (FPGA) with integrated High Bandwidth ...
The Next Platform

IBM Throws Weight Behind Phase Change Memory

There is no question that the memory hierarchy in systems is being busted wide open and that new persistent memory technology that can be byte addressable like DRAM or block addressable like storage ...
EDN

DRAM controller throughput may be the next key to SoC performance

As SoC architects make the transition from CPU-centric designs with a single major processor to multiprocessing designs in which many processing peers carry on in parallel, efficient use of external ...
Business Wire

PRO DESIGN Launches New proFPGA XCVU37P FPGA Module for Prototyping and Verification of High Bandwidth Memory Designs

MUNICH--(BUSINESS WIRE)--PRO DESIGN, leading supplier of FPGA based prototyping systems, today launched its new proFPGA XCVU37P FPGA module for its flexible proFPGA product family. This new FPGA ...