Semiconductor Engineering

Why Your FPGA Synthesis Flow Requires Verification

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL ...
Design-Reuse

A Digital Design Flow for Differential ECL High Speed Applications

This paper presents a digital design flow in order to design high performance differential Emitter Coupled Logic (ECL) circuits efficiently. The proposed flow is similar to the ordinary digital CMOS ...
Semiconductor Engineering

Beyond Human Reach: Meeting Design Targets Faster With AI-Driven Optimization

The implementation flow for semiconductor devices is all about optimizing for power, performance, area (PPA), or some combination of these attributes. The history of this flow in electronic design ...
EDN

How to achieve fast timing closure on FPGA designs

Technological advances in FPGA devices have created both application opportunities and, at the same time, tough design challenges for developers. In new devices, for example, logic routing rather than ...
EDN

Synopsys enhances FPGA synthesis – 4X speedup plus team design capabilities

It's no secret that FPGAs just keep on getting bigger, and Bigger, and BIGGER. This is obviously good news in that greater capacity means that designers can do more with them … but the downside is ...
Electronic Design

In Adding Control-Logic Support, A High-Level Synthesis Tool Goes Full Chip

High-level synthesis (HLS), or the notion of synthesizing a design into RTL from a higher level of abstraction, has been gaining currency among design teams. For some time now, there have been ...
Electronic Design

Go Abstract To Speed Up Your Design Flow

Hence, the more complex the control flow of a design, the greater the benefits of using architectural synthesis. Unlike RTL synthesis, architectural synthesis doesn't require the comprehensive ...