Semiconductor Engineering

Automate Memory Test Through A Shared Bus Interface

The use of memory-heavy IP in SoCs for automotive, artificial intelligence (AI), and processor applications is steadily increasing. However, these memory-heavy IP often have only a single access point ...
Electronic Design

Using ATE for Efficient DigRF Interface Testing

Although the term DigRF may lead to initial impressions of a digital signal somehow integrated into an RF signal path, this is not the case. DigRF is a published standard that describes a digital ...
Electronic Design

Test strategy implications on cost of test

Test strategy analysis has become increasingly important for finding ways to reduce test costs for system-on-a-chip (SoC) semiconductor devices. Every SoC device’s test flow is unique and requires a ...
FierceBiotech

Pall's New Filter Integrity Test Instrument Combines Industry-Leading Accuracy With Compact Design and Simplified Operation

PORT WASHINGTON, N.Y., April 20, 2010 - The sensitive and accurate testing of process membrane filter integrity is critical to ensuring efficient, safe pharmaceutical production and regulatory ...
Semiconductor Engineering

AI Semiconductors Require An Integrated Test Solution

The rapid proliferation of generative pre-trained transformers based on large language models (LLMs) is driving growth in the market for chips that can run the LLMs and other artificial intelligence ...