Nature

Flip Chip Packaging and Underfill Processes

Flip chip packaging represents a cutting‐edge assembly technique in which semiconductor devices are mounted upside‐down, enabling direct connection to the substrate via solder bumps. This method not ...
Semiconductor Engineering

Thermo-Mechanical Stress On Active Chiplets In A 3D-IC Heterogeneous Package Assembly

The move to heterogeneous multi-chip/chiplet products improves yield, performance and modularity while reducing power and overall product footprint. However, this shift to heterogeneous assembly also ...
EDN

MEMS: Think outside the chip… at the package level

The issue of MEMS-based system solutions and their packaging will be addressed at the MEMS Industry Group’s annual MEMS Executive Congress, which will be held in Scottsdale AZ on November 3-5, 2010, ...
Semiconductor Engineering

Addressing Stress In Heterogeneous 3D-IC Designs

The benefits of 3D IC architectures are well-documented – smaller footprints, lower power, and increased performance. However, the move to heterogeneous 3D designs also introduces a host of new ...