Optunis has announced the FIR HDL Writer 0.9.0 Beta. FIR HDL Writer is an EDA tool that generates synthesizable Verilog RTL code to make FIR filters. This RTL may be synthesized to FPGAs and ASICs.

Why use FIR filters, anyway? With the availability of easy-to-use IIR filters in Cypress Semiconductor’s PSoC Creator’s Filter tool, I’ve spent a lot of time over the years telling people the ways in ...

In considering the design option for DSP vs. FPGA it is helpful to compare both architectures in a FIR filter application, writes Reg Zatrepalek One of the most widely used digital signal-processing ...