Electronics Weekly

Using Verilog-A simulation in analogue design

A key part of any analogue design flow is having models of the components for simulation. Traditional Spice models of basic components such as transistors and capacitors written in C or C++ are ...
EDN

Assertion Methodologies for Verilog Design

Sometimes good ideas take a while to catch on in engineering practice. The use of in-line assertions to document assumptions and check for problems in RTL code is one such idea. Long ago proposed for ...
Electronic Design

Mixed-Signal Simulator Speaks Verilog-AMS

Designers today find themselves adding more and more analog and mixed-signal content to their creations. And at nanometer geometries and gigabit speeds, digital circuits begin to look more analog than ...
Design-Reuse

Synopsys VCS Verilog Simulator Incorporates Breakthrough Verification Capabilities

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 26, 2001-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced VCS(TM) 6.0.1, the latest release of the industry's ...
EDN

Analog/RF mixed signal simulator introduced by Berkeley Design Automation

Anaheim, California &#8212 Berkeley Design Automation, Inc., has introduced a SPICE accurate analog/RF mixed-signal verification based on co-simulation of its Analog FastSPICE TM circuit simulator ...
Electronic Design

Verilog Simulator Adds Full-Featured Coverage Analysis And A C/C++ Interface

The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.
Design-Reuse

Hitachi Endorses Model Technology ModelSim for Verilog Simulation

PORTLAND, Ore.--(BUSINESS WIRE)--Oct. 3, 2001--Model Technology(TM), a Mentor Graphics company, today announced that the ModelSim® hardware description language (HDL) simulator has received Verilog ...